I have to agree with hwg on this one. I don't think there is any way to modify latencies on die without doing it at the manufacturing lvl.
hwg you do mean lower temps, higher voltages right? Less noise allows for more voltage, because it causes less noise at these lower temps due to greater efficiency at the electron lvl. And higher voltages allow faster speeds.
There is a couple of things i think need to be corrected but i may be wrong. CPUs are usually not cold bugged on the intel side. Most of the time it's the north bridge that start producing errors. RAM operates much slower the CPU (except for the AMD side of this) and the north bridge has to regulate this timing difference in between the too. Ours kept failing at ~ -30c, which is about were amd processors fail at too. P35 and X38 should help that due to better man fab but who knows?
A little while back i was reading reading some neat stuff aboutP965, 680i and 975x "straps". The north bridge has a set of timings of its own, BUT it has one diffrence: The ability to change the memory timings (on the northbridge) with the fsb. Yielding better performance. A lot of people were running 1333 with a 1066 timing and it seemed to help.
This may have kind of a random structure, but my post leads to one thought.
As the latencies in a CPU are set and optimized, the may have to slow down or speed up as an attempt to keep up or slow down with the rest of the system. As the CPU get's colder, the latencies and timing may be able to slow down or speed up as needed. I don't think this applies to the physical layer, but those get faster as they get colder too.
I believe that 8GHZ was not only achieved with a lucky processor with good timings and latencies, but with components that tolerated the lower temperatures better.
EDIT: if anything doesn't make sense ask me to clarify, my thought process is a little out of order and slightly random.
EDIT EDIT:
"When you overclock the FSB, the internal NB frequency also increases (logically). The NB "Strap" is used to loosen the internal timings/frequency(?) of the northbridge to ensure it's still operating within specified levels. (i.e running stabley). The strap changes loosen the internal NB timings to allow the FSB to be pushed further (Hence supporting 1066/1333 FSB chips without pushing the NB into instable territory). The trade off is, at the strap change point (~400 FSB on the P5B for instance) you get a performance drop as the internal latencies are much higher. The performance difference is negated however as the FSB can be pushed further thanks to the looser internal latencies. "
Borrowed this from Hildand3r
bit-tech.net Forums - Ram question for aw9d max
Cooling helps keep these timings tighter. Which is why NB cooling is always somthing i have stressed. DI should be used for the NB imo
And
this
article is why im getting the P5K